A Fractionally Spaced Linear Receive Equalizer with Voltage-to-Time Conversion

被引：0

作者：

Song, Sanquan ^{[1
]}

Kim, Byungsub ^{[1
]}

Stojanovic, Vladimir ^{[1
]}

机构：

[1] MIT, Cambridge, MA 02139 USA

来源：

2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2009年

关键词：

fractionally spaced receiver equalizer;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Based on voltage-to-time conversion technique, a pseudo-differential two-way-interleaved adaptive linear receive equalizer with two 2x-oversampled feed-forward taps has been designed in a 90 nm CMOS process. It integrates equalization and phase interpolation functions into one unit to simultaneously address inter-symbol-interference (ISI) cancellation and phase synchronization in a link receiver. It operates at 4 Gbps with 8 mW power consumption, and linearity of 4.3 effective bits at 1.2 V supply.

引用

页码：222 / 223

页数：2

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