共 50 条
- [1] FPGA Implementation of AES Encryption and Decryption [J]. PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON CONTROL AUTOMATION, COMMUNICATION AND ENERGY CONSERVATION INCACEC 2009 VOLUME II, 2009, : 567 - 573
- [2] Fpga Implementation Of Image Encryption And Decryption Using AES 128-Bit [J]. PROCEEDINGS OF THE 2016 INTERNATIONAL CONFERENCE ON COMMUNICATION AND ELECTRONICS SYSTEMS (ICCES), 2016, : 156 - 160
- [4] Hardware implementation of AES encryption and decryption system based on FPGA [J]. Open Cybernetics and Systemics Journal, 2015, 9 (01): : 1373 - 1377
- [5] FPGA based Hardware Implementation of Hybrid Cryptographic Algorithm for Encryption and Decryption [J]. 2017 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, COMMUNICATION, COMPUTER, AND OPTIMIZATION TECHNIQUES (ICEECCOT), 2017, : 416 - 419
- [6] FPGA Based Hardware Implementation of AES Rijndael Algorithm for Encryption and Decryption [J]. 2016 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, AND OPTIMIZATION TECHNIQUES (ICEEOT), 2016, : 1769 - 1776
- [8] FPGA hardware acceleration of an improved chaos-based cryptosystem for real-time image encryption and decryption [J]. Journal of Ambient Intelligence and Humanized Computing, 2023, 14 : 7001 - 7022
- [9] The Implementation of the 1024-bit RSA Encryption/Decryption Algorithms Based on FPGA [J]. 2009 INTERNATIONAL SYMPOSIUM ON INTELLIGENT INFORMATION SYSTEMS AND APPLICATIONS, PROCEEDINGS, 2009, : 420 - 423
- [10] AN IMPLEMENTATION AND PERFORMANCE EVALUATION OF AN IMPROVED CHAOTIC IMAGE ENCRYPTION APPROACH [J]. 2016 INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, COMMUNICATIONS AND INFORMATICS (ICACCI), 2016, : 1458 - 1463