Bounded model checking with description logic reasoning

被引:0
|
作者
Ben-David, Shoham [1 ]
Trefler, Richard [1 ]
Weddell, Grant [1 ]
机构
[1] Univ Waterloo, David R Cheriton Sch Comp Sci, Waterloo, ON N2L 3G1, Canada
基金
加拿大自然科学与工程研究理事会;
关键词
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Model checking is a technique for verifying that a finite-state concurrent system is correct with respect to its specification. In bounded model checking (BMC), the system is unfolded until a given depth, and translated into a CNF formula. A SAT solver is then applied to the CNF formula, to find a satisfying assignment. Such a satisfying assignment, if found, demonstrates an error in the model of the concurrent system. Description Logic (DL) is a family of knowledge representation formalisms, for which reasoning is based on tableaux techniques. We show how Description Logic can serve as a natural setting for representing and solving a BMC problem. We formulate a bounded model checking problem as a consistency problem in the DL dialect ACCI. Our formulation results in a compact representation of the model, one that is linear in the size of the model description, and does not involve any unfolding of the model. Experimental results, using the DL reasoner FaCT(++), significantly improve on a previous approach that used DL reasoning for model checking.
引用
收藏
页码:60 / +
页数:3
相关论文
共 50 条
  • [1] Model Checking Using Description Logic
    Ben-David, Shoham
    Trefler, Richard
    Weddell, Grant
    [J]. JOURNAL OF LOGIC AND COMPUTATION, 2010, 20 (01) : 111 - 131
  • [2] Bounded model checking distributed temporal logic
    Peres, Augusto
    Ramos, Jaime
    Dionisio, Francisco
    [J]. JOURNAL OF LOGIC AND COMPUTATION, 2023, 33 (05) : 1022 - 1059
  • [3] Three-valued logic in bounded model checking
    Schuele, T
    Schneider, K
    [J]. THIRD ACM & IEEE INTERNATIONAL CONFERENCE ON FORMAL METHODS AND MODELS FOR CO-DESIGN, PROCEEDINGS, 2005, : 177 - 186
  • [4] From bounded to unbounded model checking for temporal epistemic logic
    Kacprzak, M
    Lomuscio, A
    Penczek, W
    [J]. FUNDAMENTA INFORMATICAE, 2004, 63 (2-3) : 221 - 240
  • [5] Encodings of bounded LTL model checking in effectively propositional logic
    Navarro-Perez, Juan Antonio
    Voronkov, Andrei
    [J]. AUTOMATED DEDUCTION - CADE-21, PROCEEDINGS, 2007, 4603 : 346 - +
  • [6] Bounded model checking for branching-time temporal logic
    Zhou Conghua
    Tao Zhihong
    Ding Decheng
    Wang Lifu
    [J]. CHINESE JOURNAL OF ELECTRONICS, 2006, 15 (04) : 675 - 678
  • [7] Model Checking Temporal Epistemic Logic under Bounded Recall
    Belardinelli, Francesco
    Lomuscio, Alessio
    Yu, Emily
    [J]. THIRTY-FOURTH AAAI CONFERENCE ON ARTIFICIAL INTELLIGENCE, THE THIRTY-SECOND INNOVATIVE APPLICATIONS OF ARTIFICIAL INTELLIGENCE CONFERENCE AND THE TENTH AAAI SYMPOSIUM ON EDUCATIONAL ADVANCES IN ARTIFICIAL INTELLIGENCE, 2020, 34 : 7071 - 7078
  • [8] Representation and Reasoning of Fuzzy ER Model with Description Logic
    Zhang, Fu
    Ma, Z. M.
    Yan, Li
    [J]. 2008 IEEE INTERNATIONAL CONFERENCE ON FUZZY SYSTEMS, VOLS 1-5, 2008, : 1360 - 1367
  • [9] Application of symbolic and bounded model checking to the verification of logic control systems
    Loeis, Kingliana
    Younis, Mohammed Bani
    Frey, Georg
    [J]. ETFA 2005: 10TH IEEE INTERNATIONAL CONFERENCE ON EMERGING TECHNOLOGIES AND FACTORY AUTOMATION, VOL 1, PTS 1 AND 2, PROCEEDINGS, 2005, : 247 - 250
  • [10] Incremental deductive & inductive reasoning for SAT-based Bounded Model Checking
    Zhang, L
    Prasad, MR
    Hsiao, MS
    [J]. ICCAD-2004: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, IEEE/ACM DIGEST OF TECHNICAL PAPERS, 2004, : 502 - 509