The noise behaviour of a DQPSK demodulator employing a PLL

This paper deals with the noise analysis of a special type of differential quadrature phase shift keying (QPSK) demodulator. The general principle of operation of this demodulator is discussed in a previous publication. The underlying assumptions are as follows: 1) the noise at the output of the phase-locked loop (PLL), which is part of the demodulator, can be regarded as Gaussian-distributed, 2) the four possible phase transitions of a QPSK modulated signal are equally likely and 3) the signal processing circuit following the demodulator allows perfect synchronization by means of the output symbol streams. The theoretical approach makes use of a generalized Taylor series representation that yields the output signal of a noise-corrupted PLL. The known probabilities of error for the individual PLL output impulses allows the demodulator's symbol error rates to be determined. In order to verify the theoretical results, a hardware implementation intended for the reception with an intermediate frequency of 479.5 MHz was realized. The measurements performed on this setup are then compared with theory.