An Enhanced Dual-Path ΔΣ A/D Converter

被引:0
|
作者
Nishida, Yoshio [1 ]
Hamashita, Koichi [2 ]
Temes, Gabor C. [3 ]
机构
[1] Toyohashi Univ Technol, Toyohashi, Aichi 4418580, Japan
[2] Asahi Kasei Microdevices Corp, Atsugi, Kanagawa 24321, Japan
[3] Oregon State Univ, Sch Elect Engn & Comp Sci, Corvallis, OR 97331 USA
来源
IEICE TRANSACTIONS ON ELECTRONICS | 2010年 / E93C卷 / 06期
关键词
ADC; delta-sigma modulation; DWA; switched-capacitor circuits; CMOS; ADC;
D O I
10.1587/transele.E93.C.884
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents an enhanced dual-path delta-sigma analog-to-digital converter. Compared with other architectures, the enhanced architecture increases the noise shaping order without any instability problems and displays analog complexity equivalent to the multi-stage noise shaping architecture. Our delta-sigma converter is based on this new architecture. It employs not only doubly-differential structure to reduce common-mode errors in the system-level but also delayed-feed-in structure to mitigate the timing constraint of the feedback signal. Regarding the circuit implementation, the first-order enhancement of the quantization noise shaping is achieved via the use of a switched capacitor circuit technique. The circuit is incorporated into the active adder in a low-distortion structure. The supporting clock generation circuit that provides additional phases of clocks with the enhancement block is also implemented in the CMOS logic gates. A digital dynamic element matching circuit (i.e., segmented data-weighted-average circuit) is designed to reduce mismatch errors caused by the feedback DAC of modulator. A test chip, fabricated in a 0.18-mu m CMOS process, provides a signal-to-noise+distortion ratio (SNDR) of 75-dB for a 1.0-MHz signal bandwidth clocked at 40-MHz. The 2nd harmonic is -101 dB and the 3rd harmonic is -94 dB when a -4.5-dB 100-kHz input signal is applied.
引用
收藏
页码:884 / 892
页数:9
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