High-speed hybrid Threshold-Boolean logic counters and compressors

In this paper we propose high-speed hybrid Threshold-Boolean logic counters and compressors employed in parallel multiplication and multiple operand addition. First, we present a depth-2 hybrid implementation scheme for arbitrary symmetric Boolean functions, based on differential Threshold logic gates as circuit style. Subsequently, we apply the previous general scheme to parallel p/q counters and p\2 compressors. Finally, we present hybrid logic designs of a 7/3 counter and a 7\2 compressor. The simulation results, suggest that the hybrid 7/3 counter and 7\2 compressor designed in .25mum CMOS, achieve between 53% and 61% higher speed when compared with traditional Boolean logic and Threshold logic counterparts, at expense of between 67% and 74% more transistors.