Nanoarrays for Systolic Biosequence Analysis

Applications like biosequence alignment are currently addressed using traditional technology at the price of a huge overhead in terms of area and power dissipation. Nanoarrays are expected to outperform current limits especially in terms of processing capabilities. The purpose of this work is to assess the real terms of these expectations. Our contribution deals with: (i) a new model for nanowire FETs used to evaluate transistor's essential performance; (ii) a new switch-level simulator for nanoarray structure used to evaluate its switching activity; (iii) a nanoarray implementation for biosequence alignment based on a systolic array and the modeling of its essential performance based on (i) and (ii); (iv) the evaluation of the potential improvement of the nanoarray-based systolic structure with respect to an equivalent CMOS one in terms of processing capabilities, area, and power dissipation. Depending on the possible technological scenario, the performance of nanoarray is impressive, especially considering the density achievable in terms of processing per unit area. A wide solution space can be explored to find the optimal solution in terms of trading power and performance considering the technological limitations of a realistic implementation.