Evaluating transient error effects in digital nanometer circuits

Radiation-induced transient errors have become a great threat to the reliability of nanometer circuits. The need for cost-effective robust circuit design mandates the development of efficient reliability metrics. We present a novel "Noise Impact Analysis" methodology to evaluate the transient error effects in static CMOS digital circuits. With both the circuit, and the transient noise abstracted in the format of matrices, the circuit-noise interaction is modeled by a series of matrix transformations. During the transformation, factors that potentially affect the propagation & capture of transient errors are modeled as matrix operations. Finally, a "Noise Capture Ratio" is computed as the probability of a sequential element capturing transient noise inside the combinational logics, It is used as a measure of the transient noise effects in the circuit. Comparison with SPICE simulation demonstrates that our technique can accurately, yet quickly estimate the probability of transient errors causing observable error effects. The proposed methodology will greatly facilitate the economic design of robust nanometer circuits.