Evaluation of Cache Coherence Protocols on Multi-Core Systems with Linear Workloads

被引:0
|
作者
Jang, Yong J. [1 ]
Ro, Won W. [1 ]
机构
[1] Yonsei Univ, Sch Elect & Elect Engn, Seoul 120749, South Korea
关键词
Multi-core; cache coherence protocol; parallel matrix mulitplication; directory coherence; token coherence;
D O I
10.1109/CCCM.2009.5267596
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
Cache coherence protocols are major factors in achieving high performance through thread-level parallelism on multi-core systems. Among them, the token coherence protocol is the most efficient cache coherence protocol in maintaining the memory consistency. We used linear workloads such as parallel matrix multiplication to evaluate the token coherence protocol against the directory coherence protocol using GEMS on Simics. The experimental results demonstrate that the token coherence protocol is a more flexible framework than the directory coherence protocol on multi-core systems because it can provide improved performance and reduced complexity. Moreover, we established the relationship between the shared cache size and total performance.
引用
收藏
页码:342 / 345
页数:4
相关论文
共 50 条
  • [1] Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems
    Kaushik, Anirudh Mohan
    Hassan, Mohamed
    Patel, Hiren
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 2021, 70 (12) : 2098 - 2111
  • [2] Analysis of Multi-core Cache Coherence Protocols from Energy and Performance Perspective
    Joshi, Amit D.
    Indrajeet, S.
    Ramasubramanian, N.
    Begum, B. Shameedha
    [J]. 2017 INTERNATIONAL CONFERENCE ON RECENT INNOVATIONS IN SIGNAL PROCESSING AND EMBEDDED SYSTEMS (RISE), 2017, : 381 - 388
  • [3] Predictable Cache Coherence for Multi-Core Real-Time Systems
    Hassan, Mohamed
    Kaushik, Anirudh M.
    Patel, Hiren
    [J]. PROCEEDINGS OF THE 23RD IEEE REAL-TIME AND EMBEDDED TECHNOLOGY AND APPLICATIONS SYMPOSIUM (RTAS 2017), 2017, : 235 - 246
  • [4] Performance Analysis of Cache Coherence Protocols for Multi-core Architectures : A System Attribute Perspective
    Joshi, Amit D.
    Vollala, Satyanarayana
    Begum, B. Shameedha
    Ramasubramanian, N.
    [J]. INTERNATIONAL CONFERENCE ON ADVANCES IN INFORMATION COMMUNICATION TECHNOLOGY & COMPUTING, 2016, 2016,
  • [5] Characterization of scientific workloads on systems with multi-core processors
    Alam, Sadaf R.
    Barrett, Richard F.
    Kuehn, Jeffery A.
    Roth, Philip C.
    Vetter, Jeffrey S.
    [J]. PROCEEDINGS OF THE IEEE INTERNATIONAL SYMPOSIUM ON WORKLOAD CHARACTERIZATION, 2006, : 225 - +
  • [6] Improving the scalability of shared cache multi-core systems
    Prabhu, Sapna
    Daruwala, R. D.
    [J]. 2014 ANNUAL IEEE INDIA CONFERENCE (INDICON), 2014,
  • [7] Comparative evaluation of multi-core cache occupancy strategies
    Su, Feiqi
    Shi, Xudong
    Liu, Gang
    Xia, Ye
    Peir, Jih-Kwon
    [J]. 2007 INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED SYSTEMS, VOLS 1 AND 2, 2007, : 209 - 216
  • [8] Research on Cache Coherence Key Technology in Multi-core Processor System
    Zhang, Su
    [J]. PROCEEDINGS OF THE 2016 4TH INTERNATIONAL CONFERENCE ON ELECTRICAL & ELECTRONICS ENGINEERING AND COMPUTER SCIENCE (ICEEECS 2016), 2016, 50 : 206 - 209
  • [9] Runtime-Guided Cache Coherence Optimizations in Multi-core Architectures
    Manivannan, Madhavan
    Stenstrom, Per
    [J]. 2014 IEEE 28TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM, 2014,
  • [10] DISCO: Time-Compositional Cache Coherence for Multi-Core Real-Time Embedded Systems
    Hassan, Mohamed
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 2023, 72 (04) : 1163 - 1177