3D simulation of process effects limiting FinFET performance and scalability

被引：0

作者：

Burenkov, A ^{[1
]}

Lorenz, J ^{[1
]}

机构：

[1] Fraunhofer Inst Integrated Syst & Device Technol, D-91058 Erlangen, Germany

来源：

SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES 2004 | 2004年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Coupled three-dimensional process and device simulations have been applied to study effects limiting the performance of FinFETs, a novel CMOS transistors suggested to overcome the limitations of conventional CMOS for gate lengths at 50 nm and below.

引用

页码：125 / 128

页数：4

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