Performance of Multigate Single Electron Transistor in Wide Temperature Range and 22 nm Hybrid Technology

This paper reflects the performance improvement of single electron transistor considering multiple gates by solving master equation. We get the electrical characteristics using SIMON simulator at room temperature and show the thermionic contribution to the direct tunneling current at high temperature. To co integrate the SET logic with CMOS technology we have used the 22 nm node simulation tools. Simulation results show a good agreement. Finally, comparison of circuit's power consumption and delay analysis has been carried out between Hybrid MGSET-MOS and conventional technology. All the simulation is done in room temperature via 22-nm BSIM4 predictive model to realize the robustness and novelty of our presented model.