A Heterogeneous PIM Hardware-Software Co-Design for Energy-Efficient Graph Processing

Processing-In-Memory (PIM) is an emerging technology that addresses the memory bottleneck of graph processing. In general, analog memristor-based PIM promises high parallelism provided that the underlying matrix-structured crossbar can be fully utilized while digital CMOS-based PIM has a faster single-edge execution but its parallelism can be low. In this paper, we observe that there is no absolute winner between these two representative PIM technologies for graph applications, which often exhibit irregular workloads. To reap the best of both worlds, we introduce a new heterogeneous PIM hardware, called Hetraph, to facilitate energy-efficient graph processing. Hetraph incorporates memristor-based analog computation units (for high-parallelism computing) and CMOS-based digital computation cores (for efficient computing) on the same logic layer of a 3D die-stacked memory device. To maximize the hardware utilization, our software design offers a hardware heterogeneity-aware execution model and a workload offloading mechanism. For performance speedups, such a hardware-software co-design outperforms the state-of-the-art by 7.54x (CPU), 1.56x (GPU), 4.13x (memristor-based PIM) and 3.05x (CMOS-based PIM), on average. For energy savings, Hetraph reduces the energy consumption by 57.58x (CPU), 19.93x (GPU), 14.02x (memristor-based PIM) and 10.48x (CMOS-based PIM), on average.