Linearity and Analog Performance Realization of Energy-Efficient TFET-Based Architectures: An Optimization for RFIC Design

被引：8

作者：

Upasana ^{[1
]}

Narang, Rakhi ^{[2
]}

Saxena, Manoj ^{[3
]}

Gupta, Mridula ^{[1
]}

机构：

[1] Univ Delhi, Dept Elect Sci, Semicond Device Res Lab, South Campus, New Delhi 110021, India

[2] Univ Delhi, Sri Venkateswara Coll, Dept Elect, New Delhi 110021, India

[3] Univ Delhi, Dept Elect, Deen Dayal Upadhyaya Coll, New Delhi 110015, India

来源：

IETE TECHNICAL REVIEW | 2016年 / 33卷 / 01期

关键词：

DMG H-D TFET; DMG TFET; H-D TFET; Linearity; Tunnel FET; TUNNEL; MOSFET;

D O I：

10.1080/02564602.2015.1043153

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The paper focuses on a comprehensive study of linearity and analog performance aspects of tunnel field effect transistor (TFET) device architectures such as dual material gate (DMG) TFET, hetero-dielectric (H-D) TFET, and dual material gate hetero-dielectric (DMG H-D) TFET. The parameters governing the device linearity and analog performance trends have been investigated in terms of transconductance (g(m1)), drain conductance (g(d1)), and second- and third-order derivatives of current, i.e., g(m2) and g(m3). Further the linearity performance of DMG H-D TFET has been optimized by tuning the metal gate length and high-k dielectric length.

引用

页码：23 / 28

页数：6

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