Surface-Potential-Based Silicon Carbide Power MOSFET Model for Circuit Simulation

被引:20
|
作者
Shintani, Michihiro [1 ]
Nakamura, Yohei [2 ]
Oishi, Kazuki [3 ]
Hiromoto, Masayuki [3 ]
Hikihara, Takashi [2 ]
Sato, Takashi [3 ]
机构
[1] Nara Inst Sci & Technol, Grad Sch Informat Sci, Nara 6300192, Japan
[2] Kyoto Univ, Grad Sch Engn, Kyoto 6068501, Japan
[3] Kyoto Univ, Grad Sch Informat, Kyoto 6068501, Japan
基金
日本科学技术振兴机构;
关键词
Compact modeling; device modeling; interface trap; SPICE simulation; 4H-SIC MOSFETS; COMPACT;
D O I
10.1109/TPEL.2018.2805808
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Transistor models have been playing a key role in designing efficient power converters. As the operating frequency of the converters becomes higher, transistor models need to represent physical device behavior accurately. This paper proposes a comprehensive surface-potential-based model of silicon carbide (SiC) power MOSFETs that realizes accurate circuit simulations. Whereas conventional simulation models are based on empirical formulas, the proposed model is constructed in a surface-potential-based framework by considering the physical structure and behavior of vertical power SiC MOSFETs. The proposed model represents both I-V and C-V characteristics from weak inversion to the high-power region. In addition, the proposed model calculates the channel mobility degradation due to SiC/SiO2 interface traps, which significantly affects the circuit performance. Through experiments using a commercial SiC power MOSFET, excellent agreements are obtained between measurement and simulation in I-V and C-V characteristics at various temperatures for wide power ranges up to 1 kW. The transient behavior of a double-pulse tester is also well reproduced within a timing error of 12.6 ns even under the high temperature.
引用
收藏
页码:10774 / 10783
页数:10
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