FPL Demo: Logic Shrinkage: A Neural Architecture Search-Based Approach to FPGA Netlist Generation

被引：0
|
作者：
Auffret, Marie [1 ]
Wang, Erwei [2 ]
Davis, James J. [1 ]
机构：
[1] Imperial Coll London, Dept Elect & Elect Engn, London, England
[2] AMD, Mountain View, CA USA
来源：
2022 32ND INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, FPL | 2022年
关键词：
D O I：
10.1109/FPL57034.2022.00086
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：470 / 470
页数：1
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