A Low-Power Area-Efficient 8 bit SAR ADC Using Dual Capacitor Arrays for Neural Microsystems

被引：2

作者：

Chang, Sun-Il ^{[1
]}

Yoon, Euisik ^{[1
]}

机构：

[1] Univ Michigan, Dept Elect Engn & Comp Sci, Ann Arbor, MI 48109 USA

来源：

2009 ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING IN MEDICINE AND BIOLOGY SOCIETY, VOLS 1-20 | 2009年

关键词：

D O I：

10.1109/IEMBS.2009.5333068

中图分类号：

R318 [生物医学工程];

学科分类号：

0831 ;

摘要：

We report an area-efficient 8bit SAR ADC using dual capacitor array banks for brain signal interface microsystems. The proposed ADC consumes 680nW and the total chip area is 0.035 mm(2). We reduced the area and power by a factor of eight when compared with conventional approaches. If we increase the resolution, the area and power reduction factor exponentially increases in our architecture (e.g., a factor of 16 for 10 bit resolution). The measured SNDR, SFDR, THD, and ENOB are 42.82 +/- 0.47 dB, 57.90 +/- 2.82dB, -53.58 +/- 2.15 dB, and 6.65 +/- 0.07 bits, respectively.

引用

页码：1647 / 1650

页数：4

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