user

Area optimizations for dual-rail circuits using relative-timing analysis

被引：0
|
作者：
Chelcea, Tiberiu [1 ]
Venkataramani, Girish [1 ]
Goldstein, Seth C. [1 ]
机构：
[1] Carnegie Mellon Univ, Sch Comp Sci, Pittsburgh, PA 15213 USA
来源：
ASYNC 2007: 13TH IEEE INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS | 2007年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. However, the investment in asynchronous CAD tools does not approach that in synchronous ones. Even when asynchronous tools leverage existing synchronous toolfows, they introduce large area and speed overheads. This paper proposes several heuristic and optimal algorithms, based on timing interval analysis, for improving existing asynchronous CAD solutions by optimizing area. The optimized circuits are 2.4 times smaller for an optimal algorithm and 1.8 times smaller for a heuristic one than the existing solutions. The optimized circuits are also shown to be resilient to large parametric variations, yielding better average-case latencies than their synchronous counterparts.
引用
收藏
页码：117 / +
页数：2
相关论文
共 50 条
  • [31] Modeling and verifying circuits using generalized relative timing
    Seshia, SA
    Bryant, RE
    Stevens, KS
    [J]. 11TH IEEE INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS, PROCEEDINGS, 2005, : 98 - 108
  • [32] Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic
    Cilio, Washington
    Linder, Michael
    Porter, Chris
    Di, Jia
    Thompson, Dale R.
    Smith, Scott C.
    [J]. MICROELECTRONICS JOURNAL, 2013, 44 (03) : 258 - 269
  • [33] On single/dual-rail mixed PTL/static circuits in floating-body SOI and bulk CMOS: A comparative assessment
    Cho, GR
    Chen, T
    [J]. 16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2003, : 513 - 518
  • [34] Effectiveness of Dual-Rail CSSAL against Power Analysis Attack under CMOS Process Variation
    Monteiro, Cancio
    Takahashi, Yasuhiro
    Sekine, Toshikazu
    [J]. 2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS), 2014, : 121 - 124
  • [35] Security evaluation of DPA countermeasures using dual-rail pre-charge logic style
    Suzuki, Daisuke
    Saeki, Minoru
    [J]. CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2006, PROCEEDINGS, 2006, 4249 : 255 - 269
  • [36] A logic-cell-embedded PLA (LCPLA): An area-efficient dual-rail array logic architecture
    Yamaoka, H
    Yoshida, H
    Ikeda, M
    Asada, K
    [J]. IEICE TRANSACTIONS ON ELECTRONICS, 2004, E87C (02) : 238 - 245
  • [37] Masked Dual-Rail Precharge Logic Encounters State-of-the-Art Power Analysis Methods
    Moradi, Amir
    Kirschbaum, Mario
    Eisenbarth, Thomas
    Paar, Christof
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2012, 20 (09) : 1578 - 1589
  • [38] Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic
    Hanyu, T
    Ike, T
    Kameyama, M
    [J]. 2000 PACIFIC RIM INTERNATIONAL SYMPOSIUM ON DEPENDABLE COMPUTING, PROCEEDINGS, 2000, : 27 - 33
  • [39] The effectiveness of TAG or guard-gates in SET suppression using delay and dual-rail configurations at 0.35 μm
    Shuler, R. L.
    Balasubramanian, A.
    Narasimham, B.
    Bhuva, B. L.
    O'Neill, P. M.
    Kouba, C.
    [J]. IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2006, 53 (06) : 3428 - 3431
  • [40] Comparative Performance Analysis of Dual-Rail Domino Logic and CMOS Logic Under Near-Threshold Operation
    Maruyama, Tsuyoshi
    Hamada, Mototsugu
    Kuroda, Tadahiro
    [J]. 2018 IEEE 61ST INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2018, : 25 - 28
12345