Simulation based cause and effect analysis of cycle time and WIP in semiconductor wafer fabrication

被引：0

作者：

Qi, C ^{[1
]}

Tang, TK ^{[1
]}

Sivakumar, AI ^{[1
]}

机构：

[1] Nanyang Technol Univ, Sch Mech & Prod Engn, Singapore 639798, Singapore

来源：

PROCEEDINGS OF THE 2002 WINTER SIMULATION CONFERENCE, VOLS 1 AND 2 | 2002年

关键词：

D O I：

暂无

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

Semiconductor wafer fabrication, is perhaps one of the most complex manufacturing processes found today. In this paper, we construct a simulation model of part of a wafer fab using ProModel(R) software-a-rid. analyze the effect of different input variables on selected parameters, such as cycle time, WIP level and equipment utilization rates. These input variables include: arrival distribution, batch size, downtime pattern and lot release control. SEMATECH DATASET which has the original actual wafer fab data is used-for our analysis.

引用

页码：1423 / 1430

页数：8

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