Investigation of low-power low-voltage circuit techniques for a hybrid full-adder cell

被引：0
|
作者：
Hassoune, I
Neve, A
Legat, JD
Flandre, D
机构：
[1] Univ Catholique Louvain, Dice, B-1348 Louvain, Belgium
[2] IBM Entwicklung, D-71032 Boblingen, Germany
来源：
INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION | 2004年 / 3254卷
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A full-adder implemented by combining branch-based logic and pass-gate logic is presented in this contribution. A comparison between this proposed full-adder (named BBL_PT) and its counterpart in conventional CMOS logic, was carried out in a 0.13mum PD (partially depleted) SOI CMOS for a supply voltage of 1.2V and a threshold voltage of 0.28V. Moreover, MTCMOS (multi-threshold) circuit technique was applied on the proposed full-adder to achieve a trade-off between Ultra-Low power and high performance design. Design with DTMOS (dynamic threshold) devices was also investigated with two threshold voltage values (0.28V and 0.4V) and V-dd = 0.6V.
引用
收藏
页码：189 / 197
页数：9
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