Comparison of graphical and sub-expression elimination methods for design of efficient multipliers

被引：0

作者：

Dempster, AG ^{[1
]}

Macleod, MD ^{[1
]}

Gustafsson, O ^{[1
]}

机构：

[1] Univ Westminster, London W1W 6UW, England

来源：

CONFERENCE RECORD OF THE THIRTY-EIGHTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, VOLS 1 AND 2 | 2004年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Relationships are examined between two traditional strategies used to design "multiplier blocks": graphical methods and common subexpression elimination (CSE) Four applications: single multipliers, multiplier blocks (several products of a single multiplicand), FIR filters, and matrix multipliers are compared. A new representation shows how graphical designs can be extracted from CSE designs. Algorithms for both approaches are compared. A new graphical algorithm for FIR filter design, and new results for CSE in the multiple product case are presented so comparison can be made for All applications. We conclude that for simpler problems, graphical methods are best, while CSE works better for the more complex problems.

引用

页码：72 / 76

页数：5