Efficient and accurate modeling of power supply noise on distributed on-chip power networks

被引：0

作者：

Zheng, LR ^{[1
]}

Li, BX ^{[1
]}

Tenhunen, H ^{[1
]}

机构：

[1] Royal Inst Technol, Dept Elect, Elect Syst Design Lab, S-16440 Kista, Sweden

来源：

ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL II: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY | 2000年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we propose an efficient and accurate modeling technique for power supply noise estimation over on-chip power lines which are modeled as distributed RCL networks. With this model, peak noise on the power lines that includes on-chip resistive and inductive voltage drops, switching noise on packages, and on-chip decoupling effects, can be computed very efficiently and accurately. The model is verified by SPICE simulations.

引用

页码：513 / 516

页数：4

共 50 条

[31] Evaluation of PDN Impedance and Power Supply Noise for Different On-Chip Decoupling Structures
Fujita, Haruya
Takatani, Hiroki
Tanaka, Yosuke
Kawaguchi, Shohei
Sato, Masaomi
Sudo, Toshio
[J]. 2013 9TH INTERNATIONAL WORKSHOP ON ELECTROMAGNETIC COMPATIBILITY OF INTEGRATED CIRCUITS (EMC COMPO 2013), 2013, : 142 - 146
[32] On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip
Liu, Weichen
Wang, Yu
Wang, Xuan
Xu, Jiang
Yang, Huazhong
[J]. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2013, 24 (04) : 767 - 777
[33] Impact of on-chip inductance on power supply integrity
Eireiner, M.
Henzler, S.
Zhang, X.
Berthold, J.
Schmitt-Landsiedel, D.
[J]. ADVANCES IN RADIO SCIENCE, 2008, 6 : 227 - 232
[34] A Technique for Analyzing On-chip Power Supply Impedance
Ishida, Masahiro
Nakura, Toru
Matsukawa, Akira
Ikeno, Rimon
Asada, Kunihiro
[J]. 2015 IEEE 24TH ASIAN TEST SYMPOSIUM (ATS), 2015, : 193 - 198
[35] Power efficient photonic networks on-chip - art. no. 689813
Bergman, Keren
Carloni, Luca
[J]. SILICON PHOTONICS III, 2008, 6898 : 89813 - 89813
[36] Scaling trends of on-chip power distribution noise
Mezhiba, AV
Friedman, EG
[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2004, 12 (04) : 386 - 394
[37] Design Considerations of Distributed and Centralized Switched-Capacitor Converters for Power Supply On-Chip
Lu, Yan
Jiang, Junmin
Ki, Wing-Hung
[J]. IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, 2018, 6 (02) : 515 - 525
[38] Power and Jitter Optimized VCO Design Using an On-Chip Supply Noise Monitoring Circuit
Liu, Yutao
Xu, Ni
Rhee, Woogeun
Wang, Ziqiang
Wang, Zhihua
[J]. PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS), 2010, : 935 - 938
[39] Modeling and Tools for Power Supply Variations Analysis in Networks-on-Chip
Dahir, Nizar S.
Mak, Terrence
Xia, Fei
Yakovlev, Alexandre
[J]. IEEE TRANSACTIONS ON COMPUTERS, 2014, 63 (03) : 679 - 690
[40] Minimizing Power Supply Noise Through Harmonic Mappings in Networks-on-Chip
Dahir, Nizar
Mak, Terrence
Xia, Fei
Yakovlev, Alex
[J]. CODES+ISSS'12:PROCEEDINGS OF THE TENTH ACM INTERNATIONAL CONFERENCE ON HARDWARE/SOFTWARE-CODESIGN AND SYSTEM SYNTHESIS, 2012, : 113 - 122

← 1 2 3 4 5 →