User-friendly verification

被引:0
|
作者
Hsiung, PA [1 ]
Wang, F [1 ]
机构
[1] Acad Sinica, Inst Informat Sci, Taipei, Taiwan
关键词
timed automata; TCTL; model-checking; state-space explosion; verification tool; concurrent real-time systems;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Model checking often faces the problem of reducing the large exponential sizes of state-space representations. Several reduction techniques such as bisimulation equivalence, partial-order semantics, and symmetry-based reduction have been proposed, but existing tools do not completely allow a user the flexibility in manipulating state spaces. We propose a new user-friendly verification environment where a user has full control on what techniques to apply and in what sequences to apply them. We have implemented the environment in a tool called State-Graph Manipulators (SGM). SGM packages verification techniques into efficient, reusable, modular manipulators, that act on high-level state-space representations called state-graphs. Further, we are also proposing four new state space reduction techniques, namely variable shielding, read-write analysis, internal transitions bypassing, and sibling transition multiplicity reduction. They are implemented into SGM and experiments have been conducted to show their usefulness.
引用
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页码:279 / 294
页数:16
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