Selectively-formed high mobility SiGe-on-Insulator pMOSFETs with Ge-rich strained surface channels using local condensation technique

被引：0

作者：

Tezuka, T ^{[1
]}

Nakaharai, S ^{[1
]}

Moriyama, Y ^{[1
]}

Sugiyama, N ^{[1
]}

Takagi, S ^{[1
]}

机构：

[1] MIRAI, ASET, Saiwai Ku, Kawasaki, Kanagawa 2128582, Japan

来源：

2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2004年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new approach to selectively form strained SiGe-onInsulator (SGOI) channel transistors with very high Ge fraction on an SOI substrate is demonstrated. This method consists of epitaxial growth of SiGe layer with low Ge fraction and local oxidation processes. The obtained SGOI-pMOSFET with a Ge fraction of 93% has exhibited mobility enhancement up to 10 times. The thickness scalability of the SGOI channels was also confirmed down to 5 nm.

引用

页码：198 / 199

页数：2

共 17 条

[11] High-performance uniaxially strained SiGe-on-insulator pMOSFETs fabricated by lateral-strain-relaxation technique
Irisawa, Toshifurni
Numata, Toshinori
Tezuka, Tsutormt
Usuda, Koji
Hirashita, Norio
Sugiyama, Naoharu
Toyoda, Eiji
Takagi, Shin-Ichi
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (11) : 2809 - 2815
[12] Influence of SiGe layer thickness and Ge fraction on compressive strain and hole mobility in a SiGe-on-insulator substrate fabricated by the Ge condensation technique
Yang, Haigui
Wang, Dong
Nakashima, Hiroshi
THIN SOLID FILMS, 2012, 520 (08) : 3283 - 3287
[13] Strain analysis in ultrathin SiGe-on-insulator layers formed from strained Si-on-insulator substrates by Ge-condensation process
Tezuka, Tsutomu
Hirashita, Norio
Moriyama, Yoshihiko
Nakaharai, Shu
Sugiyama, Naoharu
Takagi, Shin-ichi
APPLIED PHYSICS LETTERS, 2007, 90 (18)
[14] Evidence for existence of deep acceptor levels in SiGe-on-insulator substrate fabricated using Ge condensation technique
Yang, Haigui
Wang, Dong
Nakashima, Hiroshi
APPLIED PHYSICS LETTERS, 2009, 95 (12)
[15] Surface Ge-rich p-type SiGe channel tunnel field-effect transistor fabricated by local condensation technique
Lee, Junil
Lee, Ryoongbin
Kim, Sihyun
Lee, Kitae
Kim, Hyun-Min
Kim, Soyoun
Kim, Munhyeon
Kim, Sangwan
Lee, Jong-Ho
Park, Byung-Gook
SOLID-STATE ELECTRONICS, 2020, 164
[16] Ge-rich (70%) SiGe nanowire MOSFET fabricated using pattern-dependent Ge-condensation technique
Jiang, Y.
Singh, N.
Liow, T. Y.
Loh, W. Y.
Balakumar, S.
Hoe, K. M.
Tung, C. H.
Bliznetsov, V.
Rustagi, S. C.
Lo, G. Q.
Chan, D. S. H.
Kwong, D. L.
IEEE ELECTRON DEVICE LETTERS, 2008, 29 (06) : 595 - 598
[17] High Performance SiGe Body-On-Insulator (BOI) FinFET Fabricated on Bulk Si Substrate Using Ge Condensation Technique
Ren, Zhexuan
An, Xia
Zhang, Bingxin
Sun, Shuang
Gao, Fei
Li, Ming
Zhang, Xing
Huang, Ru
IEEE ELECTRON DEVICE LETTERS, 2020, 41 (09) : 1280 - 1283

← 1 2 →