Analytical Analysis of the MCUs Sensitiveness of TMR Architectures in SRAM-based FPGAs

In this paper we present an analytical analysis of the fault masking capabilities of Triple Modular Redundancy (TMR) hardening technique in the presence of Multiple Cell Upsets (MCUs) in the configuration memory of SRAM-based FPGAs. The analytical method we developed allow an accurate study of the MCUs sensitiveness characterizing the orientation and the effects provoking multiple domain crossing errors that defeats the TMR fault tolerance capability. From our analysis we have found that most of the failure affects configurable logic block's routing resources. The experimental analysis have been performed on two realistic case study circuits. Experimental results are presented and discussed in terms of faults effects showing in particular that 2-bits MCUs may corrupt TMR 2.6 order of magnitude more than Single Cell Upsets (SCUs).