Soft-Error-Immune Read-Stability-Improved SRAM for Multi-Node Upset Tolerance in Space Applications

With aggressive scaling of transistor size and supply voltage, the critical charge of the sensitive nodes is reducing rapidly. As a result, when these deep submicron devices are used in memory cells in the space environment, single-event upsets (SEUs), also known as soft-errors, pose a great threat to the reliability of the cells. To mitigate the effects of SEUs, we propose a soft-error-immune read-stability-improved (SIRI) SRAM cell. To assess the performance of the proposed cell, it is compared with other soft-error-immune SRAM cells, namely, QUCCE12T, WE-QUATRO, RHPD12T, RHBD14T and RSP14T. Simulation results confirm that the detrimental effects of SEUs do not alter the state of SIRI as all the sensitive nodes can reattain their initial states after being impacted by an SEU. The cell can also recover from single-event multi-node upsets (SEMNUs) that occur at its storage node-pair. Moreover, the storage nodes of the proposed cell are isolated from the bitlines during read operation. Hence, it exhibits the highest read stability. The write ability and write delay of SIRI are also superior to those of the majority of the comparison cells, and it consumes much lower hold power than many of the conventional SRAM cells. All these improvements are brought about only at the expense of a slightly longer read delay.