A Study on Millisecond Annealing (MSA) Induced Layout Dependence for Flash Lamp Annealing (FLA) and Laser Spike Annealing (LSA) in Multiple MSA Scheme with 45 nm High-Performance Technology

被引：0

作者：

Miyashita, T. ^{[1
]}

Kubo, T. ^{[1
]}

Kim, Y. S. ^{[1
]}

Nishikawa, M. ^{[1
]}

Tamura, Y. ^{[1
]}

Mitani, J. ^{[1
]}

Okuno, M. ^{[1
]}

Tanaka, T. ^{[1
]}

Suzuki, H. ^{[1
]}

Sakata, T. ^{[1
]}

Kodama, T. ^{[1
]}

Itakura, T. ^{[1
]}

Idani, N. ^{[1
]}

Mori, T. ^{[1
]}

Sambonsugi, Y. ^{[1
]}

Shimizu, A. ^{[1
]}

Kurata, H. ^{[1
]}

Futatsugi, T. ^{[1
]}

机构：

[1] Fujitsu Microelect Ltd, Kuwana, Mie 5110192, Japan

来源：

2009 IEEE INTERNATIONAL ELECTRON DEVICES MEETING | 2009年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We investigated the dependence of temperature uniformity dufing millisecond annealing (MSA) on the pattern density and its effect on device characteristics and static random access memory (SRAM) yields with 45-nm node technology. By comparing flash lamp annealing (FLA) and laser spike annealing (LSA), we found FLA was difficult to use in our multiple MSA scheme without absorbing layers because of its high temperature uniformity sensitivity to pattern density. LSA was found to be more promising due to its lower sensitivity to pattern density and higher potential for enhancing performance. We also found hot spots were generated during LSA; however, these can easily be avoided by introducing LSA-friendly design rules.

引用

页码：23 / 26

页数：4

共 4 条

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Iwai, M.
Imai, K.
Nagashima, N.
Kuwata, T.
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2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, : 281 - +
[2] Junction profile engineering with a novel multiple laser spike annealing scheme for 45-nm node high performance and low leakage CMOS technology
Yamamoto, T.
Kubo, T.
Sukegawa, T.
Takii, E.
Shimamune, Y.
Tamura, N.
Sakoda, T.
Nakamura, M.
Ohta, H.
Miyashita, T.
Kurata, H.
Satoh, S.
Kase, M.
Sugii, T.
2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, : 143 - +
[3] Advantages of a new scheme of junction profile engineering with laser spike annealing and its integration into a 45-nm node high performance CMOS technology
Yamamoto, T.
Kubo, T.
Sukegawa, T.
Katakami, A.
Shimamune, Y.
Tamura, N.
Ohta, H.
Miyashita, T.
Sato, S.
Kase, M.
Sugii, T.
2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2007, : 122 - +
[4] A Comparative Study of Non-melt Laser Spike Annealing and Flash Lamp Annealing in Terms of Transistor Performance and Pattern Effects on SOI-CMOSFETs for the 32 nm Node and Below
Illgen, R.
Flachowsky, S.
Herrmann, T.
Feudel, T.
Thron, D.
Bayha, B.
Klix, W.
Horstmann, M.
Stenzel, R.
ULIS 2009: 10TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION OF SILICON, 2009, : 157 - +

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