Improving wafer fab productivity with efficient floor layouts

被引:0
|
作者
Padillo, JM [1 ]
Meyersdorf, D [1 ]
机构
[1] TEFEN USA, Foster City, CA 94404 USA
关键词
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暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
As the cost of building a new fab approaches $2 billion, semiconductor manufacturers are analyzing all factors that influence profitability. Production floor layout design can significantly increase product fabrication and material-handling efficiency. Recent studies have estimated that a 10-30% reduction in manufacturing operating expenses can be realized through redesigning floor layouts [1]. In fact, if optimal layout designs were implemented throughout all industries, the annual manufacturing productivity in the US alone would increase approximately three times more than it has in any year over the last decade [2]. The semiconductor industry is no exception.
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页码:59 / +
页数:4
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