A 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS

被引：4

作者：

Tsuchiya, Akira ^{[1
]}

Hiratsuka, Akitaka ^{[2
]}

Tanaka, Kenji ^{[3
]}

Fukuyama, Hiroyuki ^{[3
]}

Miura, Naoki ^{[3
]}

Nosaka, Hideyuki ^{[3
]}

Onodera, Hidetoshi ^{[2
]}

机构：

[1] Univ Shiga Prefecture, Dept Elect Syst Engn, Hikone, Shiga, Japan

[2] Kyoto Univ, Dept Commun & Comp Engn, Kyoto, Japan

[3] NTT Corp, NTT Device Technol Labs, Atsugi, Kanagawa, Japan

来源：

32ND IEEE INTERNATIONAL SYSTEM ON CHIP CONFERENCE (IEEE SOCC 2019) | 2019年

关键词：

optical communication; transimpedance amplifier; inductive peaking;

D O I：

10.1109/SOCC46988.2019.1570548520

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper demonstrates a small area, high speed and low power CMOS transimpedance amplifier (TIA) for optical communication. To determine design parameters of multi-stage inverter-type TIA (INV-TIA) with peaking inductors, we derive a simplified model of the bandwidth and the energy per hit. Based on the bandwidth and energy per hit estimation, we designed a 5-stage INV-TIA and on-chip inductors for inductive peaking. The TIA is fabricated in a 65-nm CMOS and it operates at 45 Gb/s with 49 dB Omega transimpedance gain and 4.4 mW power consumption. The TIA achieves 98 fJ/bit energy efficiency. Small footprint design of inductors realizes the area of 0.02 mm(2) though three inductors are used.

引用

页码：150 / 154

页数：5

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