CMOS Current-Reversing Circuit

In this paper, a CMOS current-reversing circuit has been proposed. The layout of the proposed circuit has been made by using the N-well 0.35 mu m 2p4m process parameters. According to the post-layout simulation results, as the supply voltage is set to 2V, the input current range of the proposed current-reversing circuit can he +/- 150 mu A, the corresponding output linear error is less than 2%, and the output offset current is only -0.321 mu A. Moreover, the maximum power consumption is 0.42mW and when the input current is 120 mu A, the 3-dB bandwidth can be 120 MHz. Simulation results are consistent with the theoretic analysis. The proposed circuit is expected to be useful in current-mode circuits design and other related applications.