共 5 条
- [1] A 9 to 12.1GHz Sub-Sampling ADPLL Based on a Stochastic Flash TDC and a DCO with a "Folded" Common-Mode Resonator Exhibiting Less Than 90fs Jitter and a Peak FoMj of-248dB in 16nm FinFet CMOS EURAD 2020 THE 17TH EUROPEAN RADAR CONFERENCE, 2021,
- [2] A 9 to 12.1GHz Sub-Sampling ADPLL Based on a Stochastic Flash TDC and a DCO with a "Folded" Common-Mode Resonator Exhibiting Less Than 90fs Jitter and a Peak FoMj of-248dB in 16nm FinFet CMOS EURAD 2020 THE 17TH EUROPEAN RADAR CONFERENCE, 2021,
- [3] A 9 to 12.1GHz Sub-Sampling ADPLL Based on a Stochastic Flash TDC and a DCO with a "Folded" Common-Mode Resonator Exhibiting Less Than 90fs Jitter and a Peak FoMj of-248dB in 16nm FinFet CMOS 2020 50TH EUROPEAN MICROWAVE CONFERENCE (EUMC), 2020,
- [4] A 9 to 12.1 GHz Sub-Sampling ADPLL based on a Stochastic Flash TDC and a DCO with a "Folded" Common-Mode Resonator Exhibiting less than 90fs Jitter and a peak FoMj of-248 dB in 16nm FinFet CMOS 2020 50TH EUROPEAN MICROWAVE CONFERENCE (EUMC), 2020, : 1190 - 1193
- [5] A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS 2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2021, 64 : 452 - +