A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS

被引：29

作者：

Thaller, Edwin ^{[1
]}

Levinger, Run ^{[2
]}

Shumaker, Evgeny ^{[2
]}

Farber, Aryeh ^{[2
]}

Bershansky, Sergey ^{[2
]}

Geron, Nir ^{[2
]}

Ravi, Ashoke ^{[3
]}

Banin, Rotem ^{[2
]}

Kadry, Jasmin ^{[2
]}

Horovitz, Gil ^{[2
]}

Krassnitzer, Christian ^{[1
]}

Duller, Christoph ^{[1
]}

Torta, Patrick ^{[1
]}

Elzinga, Mark ^{[4
]}

Azadet, Kamran ^{[5
]}

机构：

[1] Intel, Villach, Austria

[2] Intel, Tel Aviv, Israel

[3] Intel, Hillsboro, OR USA

[4] Intel, Folsom, CA USA

[5] Intel, Santa Clara, CA USA

来源：

2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC) | 2021年 / 64卷

关键词：

D O I：

10.1109/ISSCC42613.2021.9365775

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：452 / +

页数：3

共 5 条

[1] A 9 to 12.1 GHz Sub-Sampling ADPLL based on a Stochastic Flash TDC and a DCO with a "Folded" Common-Mode Resonator Exhibiting less than 90fs Jitter and a peak FoMj of-248 dB in 16nm FinFet CMOS
Levinger, R.
Shumaker, E.
Farber, A.
Bershansky, S.
Geron, N.
Degani, O.
Ravi, A.
Banin, R.
Banin, E.
Kadry, J.
Horovitz, G.
2020 50TH EUROPEAN MICROWAVE CONFERENCE (EUMC), 2020, : 1190 - 1193
[2] A 9 to 12.1GHz Sub-Sampling ADPLL Based on a Stochastic Flash TDC and a DCO with a "Folded" Common-Mode Resonator Exhibiting Less Than 90fs Jitter and a Peak FoMj of-248dB in 16nm FinFet CMOS
Levinger, R.
Shumaker, E.
Farber, A.
Bershansky, S.
Geron, N.
Degani, O.
Ravi, A.
Banin, R.
Banin, E.
Kadry, J.
Horovitz, G.
EURAD 2020 THE 17TH EUROPEAN RADAR CONFERENCE, 2021,
[3] A 9 to 12.1GHz Sub-Sampling ADPLL Based on a Stochastic Flash TDC and a DCO with a "Folded" Common-Mode Resonator Exhibiting Less Than 90fs Jitter and a Peak FoMj of-248dB in 16nm FinFet CMOS
Levinger, R.
Shumaker, E.
Farber, A.
Bershansky, S.
Geron, N.
Degani, O.
Ravi, A.
Banin, R.
Banin, E.
Kadry, J.
Horovitz, G.
2020 50TH EUROPEAN MICROWAVE CONFERENCE (EUMC), 2020,
[4] A 9 to 12.1GHz Sub-Sampling ADPLL Based on a Stochastic Flash TDC and a DCO with a "Folded" Common-Mode Resonator Exhibiting Less Than 90fs Jitter and a Peak FoMj of-248dB in 16nm FinFet CMOS
Levinger, R.
Shumaker, E.
Farber, A.
Bershansky, S.
Geron, N.
Degani, O.
Ravi, A.
Banin, R.
Banin, E.
Kadry, J.
Horovitz, G.
2020 50TH EUROPEAN MICROWAVE CONFERENCE (EUMC), 2020,
[5] A 9 to 12.1GHz Sub-Sampling ADPLL Based on a Stochastic Flash TDC and a DCO with a "Folded" Common-Mode Resonator Exhibiting Less Than 90fs Jitter and a Peak FoMj of-248dB in 16nm FinFet CMOS
Levinger, R.
Shumaker, E.
Farber, A.
Bershansky, S.
Geron, N.
Degani, O.
Ravi, A.
Banin, R.
Banin, E.
Kadry, J.
Horovitz, G.
EURAD 2020 THE 17TH EUROPEAN RADAR CONFERENCE, 2021,

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