In DSM regime, due to higher interconnect densities, the coupling noise between adjacent signals is aggravated and can lead to many timing violations. In traditional high-level synthesis (HLS), due to lack detailed physical details, it is difficult to accurately estimate crosstalk. Crosstalk minimization is typically done during routing, which makes it computationally expensive to be used within an iterative design flow In this paper we propose a floorplan driven high-level synthesis framework for minimizing crosstalk in a bus-based architecture. The proposed framework employs a Simulated Annealing engine to simultaneously explore HLS (scheduling, allocation, and binding) and floorplan (module swap, module move, and module rotate) subspaces. The effect of a high-level decision is evaluated by updating the floorplan and identifying crosstalk prone buses (i.e., those buses exceeding L-crit). The primary goal is to minimize the number of crosstalk violations with minimum area and latency overheads. We have validated the approach by synthesizing netlists down to layout-level using Cadence-SOC encounter followed by detailed crosstalk noise analysis using Cadence Celtic. Experimental results for three DSP benchmarks (DCT, EWF, and FFT) demonstrate that the proposed approach can reduce crosstalk violations by as much as 96% (in 180 nm technology node) with an average reduction of 75% over the designs synthesized with traditional sequential flow.
