An amplitude detector for variable frequency sinusoidal signals

被引：0

作者：

Raksachat, Pariwat ^{[1
]}

Chaikla, Amphawan ^{[1
]}

Kaewpoonsuk, Anucha ^{[2
]}

Riewruja, Vanchai ^{[1
]}

Julsereewong, Prasit ^{[1
]}

机构：

[1] King Mongkut Inst Technol, Fac Engn, Bangkok, Thailand

[2] Naresuan Univ, Fac Sci, Dept Phys, Phitsanulok, Thailand

来源：

2006 SICE-ICASE INTERNATIONAL JOINT CONFERENCE, VOLS 1-13 | 2006年

关键词：

amplitude detector; peak detector; sample-and-hold circuit;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a JK-flip-flop-based logic circuit is described. Using two output signals of this designed logic circuit to control a buffered peak detector followed by a simple sample-and-hold circuit in sequential operation, a sinusoidal amplitude detector is proposed. The proposed detector allows the frequency of input signals to be varied over a wide range. Experimental results verifying the performances of the proposed circuit are in close agreement with the expected values.

引用

页码：1022 / +

页数：2

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