A parallel processing hardware architecture for Elliptic Curve Cryptosystems

被引：0

作者：

Sakiyama, Kazuo ^{[1
]}

De Mulder, Elke ^{[1
]}

Preneel, Bart ^{[1
]}

Verbauwhede, Ingrid ^{[1
]}

机构：

[1] Katholieke Univ Leuven, ESAT COSIC, B-3001 Louvain, Belgium

来源：

2006 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING, VOLS 1-13 | 2006年

关键词：

D O I：

暂无

中图分类号：

O42 [声学];

学科分类号：

070206 ; 082403 ;

摘要：

We propose a parallel processing crypto-processor for Elliptic Curve Cryptography (ECC) to speed tip EC point multiplication. The processor consists of a controller that dynamically checks instruction-level parallelism (ILP) and multiple sets of modular arithmetic logic units accelerating modular operations. A case study of HW design with the proposed architecture shows that EC point multiplication over GF(p) and GF(2(m)) can be improved by a factor of 1.6 compared to the case of using single processing element.

引用

页码：3355 / 3358

页数：4

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