FPGA based hardware acceleration for elliptic curve public key cryptosystems

被引:9
|
作者
Ernst, M [1 ]
Henhapl, B [1 ]
Klupsch, S [1 ]
Huss, S [1 ]
机构
[1] Tech Univ Darmstadt, Integrated Circuits & Syst Lab, D-64283 Darmstadt, Germany
关键词
public key cryptography; VHDL model generator; co-processor synthesis; FPGA-based hardware acceleration; ECDSA; !text type='Java']Java[!/text; JCA;
D O I
10.1016/S0164-1212(03)00075-X
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
This paper addresses public key cryptosystems based on elliptic curves, which are aimed to high-performance digital signature schemes. Elliptic curve algorithms are characterized by the fact that one can work with considerably shorter keys compared to the RSA approach at the same level of security. A general and highly efficient method for mapping the most time-critical operations to a configurable co-processor is proposed. By means of real-time measurements the resulting performance values are compared to previously published state of the art hardware implementations. A generator based approach is advocated for that purpose which supports application specific co-processor configurations in a flexible and straight forward way. Such a configurable CryptoProcessor has been integrated into a Java-based digital signature environment resulting in a considerable increase of its performance. The outlined approach combines in an unique way the advantages of mapping functionality to either hardware or software and it results in high-speed cryptosystems which are both portable and easy to update according to future security requirements. (C) 2003 Elsevier Inc. All rights reserved.
引用
收藏
页码:299 / 313
页数:15
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