Optimizing high speed flip-flop using genetic algorithm

In this paper, the optimization of power-delay-product (PDP) of a high-speed flip-flop via transistor sizing is presented. The optimization is performed using the genetic algorithm (GA). The flip-flop which is used in this optimization is called Modified Hybrid Latch Flip-Flop (MHLFF). The genetic algorithm is implemented in MATLAB with the fitness function expressed in terms of the power and the delay of the flip-flop. These parameters are accurately computed using Hspice for a 65nm CMOS technology. The results show a reduction of 31% in the PDP of the optimized structure compared to the flip-flop without any optimization.