Optimizing high speed flip-flop using genetic algorithm

被引：0

作者：

Aezinia, Fatemeh ^{[1
]}

Afzali-Kusha, Ali ^{[1
]}

Lucas, Caro ^{[1
]}

机构：

[1] Univ Tehran, Sch Elect & Comp Engn, Nanoelect Ctr Excellence, Tehran, Iran

来源：

2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS | 2006年

关键词：

optimization; high speed flip-flop; genetic; algorithm;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, the optimization of power-delay-product (PDP) of a high-speed flip-flop via transistor sizing is presented. The optimization is performed using the genetic algorithm (GA). The flip-flop which is used in this optimization is called Modified Hybrid Latch Flip-Flop (MHLFF). The genetic algorithm is implemented in MATLAB with the fitness function expressed in terms of the power and the delay of the flip-flop. These parameters are accurately computed using Hspice for a 65nm CMOS technology. The results show a reduction of 31% in the PDP of the optimized structure compared to the flip-flop without any optimization.

引用

页码：1787 / +

页数：2

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