共 35 条
- [24] Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect 2015 SYMPOSIUM ON VLSI TECHNOLOGY (VLSI TECHNOLOGY), 2015,
- [26] Contact Resistance Reduction to FinFET Source/Drain Using Dielectric Dipole Mitigated Schottky Barrier Height Tuning 2010 INTERNATIONAL ELECTRON DEVICES MEETING - TECHNICAL DIGEST, 2010,
- [29] Realization of silicon-germanium-tin (SiGeSn) source/drain stressors by Sn implant and solid phase epitaxy for strain engineering in SiGe channel P-MOSFETs 2008 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PROGRAM, 2008, : 128 - +
- [30] Novel Technique to Engineer Aluminum Profile at Nickel-Silicide/Silicon:Carbon Interface for Contact Resistance Reduction, and Integration in Strained N-MOSFETs with Silicon-Carbon Stressors 2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2011,