Modeling cache inconsistencies in an ATM high-speed network interface architecture

An asynchronous transfer mode (ATM) high-speed network interface employing a DMA (direct memory access) engine is modeled using the queuing theory of heterogeneous source environments. Specifically, the system bus is modeled as a multiplexer of data between the central processing unit (CPU), system cache, host memory and the interface. A two-stage queuing system is developed, fed by a multiplexed constant rate source, representing DMA accesses, and a Poisson distributed source, representing application writes. The resulting D+M/D/1 waiting time tail distribution is approximated analytically using a weighted M/D/1 queuing system and is verified by computer simulation, Data loss due to cache and memory inconsistencies encountered in the second stage is then observed for a variety of interarrival rates from the Poisson source. Based on observed results, a region of primary interest is noted where the arrival rate of DMA accesses is substantially greater than the mean arrival rate of application writes. Circumstances where the system can still effectively function with a low probability of data loss are identified.