An efficient VLSI implementation for MC interpolation of AVS standard

Advance Video Coding standard (AVS) [1] is the standard for compression and decompression in digital audio and video multimedia. The AVS Working Group was approved by the Science and Technology Department of Ministry of Information Industry of china on June 2002. AVS has employed a 4-tap interpolation FIR filter in its motion compensation (MC) part for high coding efficiency. But it is accompanied by increasing the complexity in calculation and memory access. And this problem makes MC one of the bottlenecks in the AVS system's VLSI implementation, especially for SDTV or HDTV which aggravate the problem heavily. Unfortunately, most FIR filter [3-5] have too low of input bandwidth to deal with it. In this paper, an efficient architecture for MC interpolation is described, and experimental results show that this architecture satisfies AVS decoder applications such as SDTV or HDTV.