Low temperature selective Si and Si-based alloy epitaxy for advanced transistor applications

被引：0

作者：

Kim, Yihwan ^{[1
]}

Zojaji, Ali ^{[1
]}

Ye, Zhiyuan ^{[1
]}

Lam, Andrew ^{[1
]}

Dalida, Nicholas ^{[1
]}

Sanchez, Errol ^{[1
]}

Kuppurao, Satheesh ^{[1
]}

机构：

[1] Epi KPU, Front End Prod Grp, Appl Mat, 974 E Arques Ave,M-S 81288, Sunnyvale, CA 94085 USA

来源：

TRANSISTOR SCALING- METHODS, MATERIALS AND MODELING | 2006年 / 913卷

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We have developed low temperature selective Si and Si-based alloy (SiGe and Si:C) epitaxy processes for advanced transistor fabrications. By lowering epitaxy process temperature (<= 700 degrees C), we have demonstrated elevated source/drain formation on ultra-thin (< 50 angstrom) body SOI transistors without Si agglomeration, smooth morphology of selective SiGe epitaxy with high [Ge] (> 30 %) and [B] (> 2E20 cm(-3)) concentrations, and selective Si:C epitaxy with high substitutional C concentration (> 1 %). Also, we have increased growth rate of low temperature selective epitaxy processes by optimizing process parameters by adapting non-conventional deposition method.

引用

页码：125 / +

页数：2

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