Low-power CMOS folding and interpolating ADC with a serial-parallel domino encoder

被引：0
|
作者：
Liu, Zhen [1 ]
Jia, Song [1 ]
Chen, Zhongjian [1 ]
Zhang, Xing [1 ]
Ji, Lijiu [1 ]
机构：
[1] Peking Univ, Inst Microelect, Beijing 100871, Peoples R China
来源：
2005 IEEE CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, PROCEEDINGS | 2005年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 8-bit 200MHz low-power CMOS folding and interpolating analog-to-digital converter is designed. A serial-parallel Domino encoder (SPDE) is presented to reduce power dissipation. A special two-stage interpolation network is adopted to decrease static nonlinearity error. The total power dissipation is merely 80mW at a 5V supply.
引用
收藏
页码：673 / 676
页数：4
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