An adaptive serial-parallel CAM architecture for low-power cache blocks

被引：0

作者：

Efthymiou, A ^{[1
]}

Garside, JD ^{[1
]}

机构：

[1] Univ Manchester, Dept Comp Sci, Manchester M13 9PL, Lancs, England

来源：

ISLPED'02: PROCEEDINGS OF THE 2002 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN | 2002年

关键词：

CAM; cache design; VLSI; low power; low energy; asynchronous circuits;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

There is an on-going debate about which consumes less energy: a RAM-tagged associative cache with an intelligent order of accessing its tags and ways (e.g. way prediction), or a CAM-tagged high associativity cache. If a CAM search can consume less than twice the energy of reading a tag RAM, it would probably be the preferred option for low-power applications. Based on memory traces - which usually cause tag mismatch within the lower four bits - a new serial CAM organisation is proposed which consumes just 45% more than a single tag RAM read and is only 25% slower than the conventional, parallel CAM. Furthermore, it can optionally be operated as a parallel CAM, at no speed penalty, and still reduce energy consumption.

引用

页码：136 / 141

页数：6

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