A High-Efficiency Good Linearity 21 to 26.5 GHz Fully Integrated Power Amplifier Using 0.18 μm CMOS Technology

被引：0

作者：

Mosalam, H. ^{[1
,2
]}

Allam, A. ^{[1
]}

Abdel-Rahman, Adel ^{[1
]}

Kaho, T. ^{[3
]}

Jia, H. ^{[3
]}

Pokharel, Ramesh K. ^{[3
]}

机构：

[1] Egypt Japan Univ Sci & Technol, Elect & Commun Engn Dept, Alexandria 21934, Egypt

[2] Elect Res Inst, Giza 12622, Egypt

[3] Kyushu Univ, Grad Sch Informat Sci & Elect Engn, Nishi Ku, Fukuoka 8190395, Japan

来源：

2016 IEEE 59TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS) | 2016年

关键词：

Power Amplifier (PA); Power Added Efficiency (PAE);

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents the design and implementation of a 21-26.5 GHz broadband, two stages CMOS power amplifier (PA) for quasi-millimeter wave band wireless communication systems. The proposed PA is designed using staggered tuning method [1], which is employed for the first time in quasi-millimeter wave band. Moreover, source and load-pull simulation, in addition to, impedance analysis are employed to optimize the input, output, and inter-stage impedance matching circuits for maximum power added efficiency (PAE) and better linearity. The measurement results on a chip fabricated using 0.18 mu m CMOS technology shows a power gain of 10.2 +/- 0.8 dB, a maximum PAE and output gain compression point (P-Out1dB) of 10.5 dBm and 18 %, respectively, at 24 GHz while consuming 42 mW only. In addition, the PA achieved excellent low measured group delay variations of 75 +/- 22 ps.

引用

页码：501 / 504

页数：4

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