In timing signoff for leading-edge SOCs, even few-picosecond timing violations will not only increase design turnaround time, but also degrade design quality (e.g., through power increase from insertion of extra buffers). Conventional flip-flop timing models have fixed values of setup/hold times and clock-to-q (c2q) delay, with some advanced "setup-hold pessimism reduction" (SHPR) methodologies exploiting multiple setup-hold pairs in the timing model. In this work, we propose to use multiple timing models to give more flexibility at timing path boundaries, thus recovering significant "free" margins and reducing the number of timing violations that require unnecessary fixes. We exploit a flexible flip-flop timing model that captures the three-way tradeoff among setup time, hold time and c2q delay, so as to reduce pessimism in timing analysis of setup-or hold-critical paths. A sequential linear programming optimization for multiple corners is used to selectively analyze setup-or hold-critical paths with less pessimism. Further improvements are possible based on partitioning of timing paths according to different modes. We demonstrate that our method can improve worst setup/hold slack metrics over conventional signoff methods, using a set of open-source designs implemented in a 65nm foundry library. We show that opportunity for timing pessimism reduction with our approach remains significant in a 28nm FDSOI foundry library as well.
