共 19 条
- [1] Impact of optimized illumination upon simple lambda based design rules for low K1 lithography METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XV, 2001, 4344 : 797 - 808
- [2] DFM Study in Low k1 Lithography Process CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2012 (CSTIC 2012), 2012, 44 (01): : 187 - 196
- [3] Thermal aberration control for low k1 lithography OPTICAL MICROLITHOGRAPHY XX, PTS 1-3, 2007, 6520
- [4] Low k1 logic design using gridded design rules DESIGN FOR MANUFACTURABILITY THROUGH DESIGN-PROCESS INTEGRATION II, 2008, 6925
- [5] Low k1 process optimization for i-line lithography OPTICAL MICROLITHOGRAPHY XIII, PTS 1 AND 2, 2000, 4000 : 1134 - 1139
- [6] Sampling plan optimization for CD control in low k1 lithography METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XIX, PTS 1-3, 2005, 5752 : 727 - 735
- [7] CD control at low K1 optical lithography in DRAM device METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XVII, PTS 1 AND 2, 2003, 5038 : 406 - 414
- [8] Source optimization and mask design to minimize MEEF in low k1 lithography PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY XV, PTS 1 AND 2, 2008, 7028
- [9] Process latitude extension in low k1 DRAM lithography using specific layer oriented illumination design OPTICAL MICROLITHOGRAPHY XVI, PTS 1-3, 2003, 5040 : 1304 - 1309
- [10] Effect of lens aberrations on OPC model accuracy for low k1 lithography process OPTICAL MICROLITHOGRAPHY XIX, PTS 1-3, 2006, 6154 : U2025 - U2034