A bit-line leakage compensation scheme for low-voltage SRAM's

被引：5

作者：

Agawa, K ^{[1
]}

Hara, H ^{[1
]}

Takayanagi, T ^{[1
]}

Kuroda, T ^{[1
]}

机构：

[1] Toshiba Corp, System ULSI Engn Lab, Saiwai Ku, Kawasaki, Kanagawa 2128520, Japan

来源：

2000 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2000年

关键词：

D O I：

10.1109/VLSIC.2000.852854

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Bit-line leakage current of an SRAM, induced by transistor leakage at low V-th, and dependent on cell data associated with the bit-line, is detected in a pre-charge cycle and compensated for during a read/write cycle. By this scheme, V-th can be lowered to 0.23 V-DD in a 0.07 mu m/1.0V CMOS, as it was before, keeping V-th and delay scalability of the high-speed SRAM.

引用

下载

页码：70 / 71

页数：2

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