Towards a Better Lifetime for Non-Volatile Caches in Chip Multiprocessors

To address the limitations imposed by the conventional SRAM cache, the emerging Non-Volatile Memory (NVM) technologies are widely used nowadays as they provide among other things high density and low leakage. However, the weak endurance of these memory technologies limits their use as a replacement of SRAM. Further, the large intra-set write variation introduced by the application and the existing cache management policies significantly reduces the lifetime of the NVM caches. This paper proposes a technique to reduce intra-set write variation to increase the effective lifetime of the NVM caches. This is achieved by partitioning the cache into equal size windows and using different windows during the execution in order to distribute the writes evenly across the set. Full system simulation results show that our policy reduces the write variation and improves the cache lifetime by 2.1 times and 1.8 times for a single and dual core system, respectively compared to an existing policy.