50Gb/s 3.3V logic ICs in InP-HBT technology

被引：1

作者：

van der Wagt, P ^{[1
]}

Broekaert, T ^{[1
]}

Yinger, S ^{[1
]}

Zheng, S ^{[1
]}

Srivastava, N ^{[1
]}

Rogers, J ^{[1
]}

Sanders, J ^{[1
]}

Thiagarajah, R ^{[1
]}

Coccioli, R ^{[1
]}

Arnold, E ^{[1
]}

Nary, K ^{[1
]}

机构：

[1] Inphi Corp, Westlake Village, CA USA

来源：

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2004年

关键词：

D O I：

10.1109/VLSIC.2004.1346604

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

50Gb/s 3.3V InP-HBT logic ICs with 6ps rise time and 1200mVpp output swing include: D-flip-flop, double-edge triggered flip-flop, dividers, a frequency doubler, XOR/OR gates, and a 1:2 fanout buffer. The DFF has 3ps(pp) deterministic and <190fs(rms) random jitter, >270deg phase margin, and 12mV(PP) sensitivity at 40Gb/s and 10(-12) BER. The ICs dissipate 480-840mW in 1mm(2).

引用

页码：326 / 329

页数：4

共 35 条

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