Automatic synthesis of IIR SC multistage decimators

被引：0
|
作者：
Ngai, C [1 ]
Martins, RP [1 ]
机构：
[1] Macao Polytech Inst, Comp Studies Program, Rua Lu Gonzaga Gomes, Macau, Peoples R China
来源：
2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL III, CONFERENCE PROCEEDINGS | 2004年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents an automated system for the design of IIR SC multistage decimators. Through the integration of different existing programs it provides a user-friendly interface that allows the implementation of IIR SC decimators from the top filter specifications down to the circuit layout. It allows the automated design of a cascade of decimator stages in order to obtain a sufficiently high ratio between the sampling frequency and the maximum signal frequency of interest, and also simplifies the circuit through the minimization of the silicon area. Two design examples are given to demonstrate the feasibility of this approach.
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页码：287 / +
页数：3
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